1. Field of the Invention
The invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly to an insulated gate field effect transistor and a method of manufacturing an insulated gate field effect transistor having an gate electrode formed on an region ranging from a gate insulating film in an element forming region to a field insulating film in an isolation region.
2. Description of the Prior Art
In recent years, with the increasing speed of an insulated gate field effect transistor, its gate electrode has been made finer and its gate insulating film has been made thinner. Therefore, the electric field strength applied to the gate insulating film has a tendency to increase, and so it has been desired to improve the gate insulating film in dielectric strength and reliability.
By now, in order to improve a gate insulating film in dielectric strength, such a measure has been taken as decreasing interface states by adding gas containing chromium (C1) ions to oxygen (O.sub.2) when forming the gate insulating film as shown on page 747 to 752 in JAPANESE JOURNAL OF APPLIED PHYSICS Vol.14, No.6, June, 1975 by Hiromitsu SHIRAKI.
FIG. 1 is a cross-sectional view showing a hitherto insulated gate field effect transistor having a gate electrode formed on an region ranging from a gate insulating film in an element forming region to a field insulating film in an isolation region.
As shown in FIG. 1, a field oxide film 4 is formed on a part of a silicon substrate 3 in an isolation region 2 by means of local oxidation of silicon (LOCOS), and a gate oxide film 5 is formed by means of thermal oxidation on a part of the silicon substrate 3 in an element forming region 1 surrounded by the isolation region 2. At this time, in order to improve the gate oxide film 5 in dielectric strength, interface states are decreased by adding gas containing chromium ions to oxygen when forming the gate oxide film 5.
And in order to connect with elements existing in an adjoining element forming region, a gate electrode 6 is not only formed on the gate insulating film 5 in the element forming region 1 but also extended to the adjoining element forming region passing through on the field oxide film 4.
With making the gate electrode 6 finer, the gate electrode 6 needs to be made lower in resistance. For this purpose, a polycide layer composed of both a polycrystalline semiconductor layer 6a and a silicide layer 6b is used as the gate electrode 6. The polycrystalline semiconductor layer 6a is highly doped with impurities giving a certain conductive type (hereinafter referred to as conductive type impurities) in order to lower its resistance.
Besides, in FIG. 1, another reference number 7 is an interlayer insulating film and number 8 is an upper interconnection layer connected with the gate electrode 6 through a viahole 7a formed in the interlayer insulating film 7 on the gate electrode 6.
However, defects or interface states in the interface region between the field oxide film 4 and the gate oxide film 5 are not decreased in the same manner as decrease of defects or interface states in the element forming region 1.
The reason is thought that the stress which is caused by heating when forming the gate oxide film 5 is applied to the field oxide film 4 and left.
Thus, dielectric strength and reliability of the insulated gate field effect transistor are governed by defects and the like generated in the interface region in spite of improving the film quality of the gate oxide film 5.
Therefore, it has been desired to further improve dielectric strength and reliability of the insulated gate field effect transistor.